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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/9414

    Title: A charge pump circuit by using voltage-doubler as clock scheme
    Authors: 黃文昌
    Wen Chang Huang
    Po Chih Liou
    Keng Yu Lin
    Jin Chang Cheng
    Contributor: 電子工程學系
    Keywords: charge pump
    high voltage clock generator
    voltage doubler
    Date: 2010-03-15
    Issue Date: 2010-03-15 14:50:42 (UTC+8)
    Abstract: A new charge pump circuit with a clock that shows
    an increased clock voltage as its stage is increased is proposed in
    the paper. The charge pump circuit utilizes the cross-connected
    NMOS, voltage doubler, as a pumping stage. Each stage of the
    voltage-doubler provides a pair of complementary clock voltages.
    The clock voltage also increases as the stage of voltage doubler is
    increased. It shows that a voltage up to 37.85V was obtained
    after eight-stage’s pumping of the circuit, through the simulation
    of HSpice under 0.35 μm process with 2V of supply voltage and
    clock voltage.
    Appears in Collections:[電子工程系所] 期刊論文

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