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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/3484


    Title: A Single-Stream Pipelined Instruction Decompression System for Embedded Microprocessors
    Authors: JeangYuan-Long (蔣元隆)
    WeyTzuu-Shaang
    WangHung-Yu
    TaiChih-Chung
    Date: 2006-12-18
    Issue Date: 2009-08-15 00:02:26 (UTC+8)
    Abstract: For instruction decompression, techniques such as single buffering, double buffering and pipelining have been proposed. However, due to jumping penalty, these techniques incur more delays in pipeline or system has to be stopped to refill the cache buffers. A Pipeline with Back-up for Flushing (PBF) technique has been developed that incurs no delay and without stopping due to jumping. However, the first instruction of each basic block should not be compressed and be put in another ROM, and thus the compression ratio should be sacrificed. This paper improves the PBF technique such that a single program ROM needed only. The simulation results for several benchmarks show that the average compression ratio is decreased about 11%, and the hardware cost deceased about 8%.
    Relation: IEEE IIH-MSP 2006, 18-20 December, 2006, California USA
    Appears in Collections:[資訊工程系所] 會議論文

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