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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/14286

    Title: An Efficient Task Scheduling Algorithm for Partial Reconfigurable FPGA-Based Systems
    Authors: Trong-Yen Lee
    Chieh-I Yu
    Yang-Hsin Fang
    Chia-Chun Tsai
    Rong-Shue Hsiao
    Keywords: Scheduling
    Reconfigurable Systems
    Date: 2007-09-28
    Issue Date: 2007-10-01 16:56:00 (UTC+8)
    Abstract: Partial reconfigurable hardware is increasingly used in embedded systems. The hardware allows partial reconfiguration at runtime that is a powerful, flexible way to deal with tasks in a limited chip capacity. While partial reconfigurable hardware enables additional application performance, it is important to take scheduling and placement into account while mapping application tasks to such architectures. We propose a task scheduling algorithm, namely STEA, can efficiently find a minimum execution time under data dependence constraints. The STEA algorithm uses datareuse concept to decrease reconfiguration power if task execute the same function. The experiment results show that proposed STEA algorithm can have efficient execution time and save average reconfiguration power up to 5% under 600 tasks in a partial reconfigurable FPGA system.
    Appears in Collections:[電子工程系所] 2007年系統雛型與電路設計創新應用研討會

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