This paper presents a reusable pulse detector to reduce the unnecessary signal passing through in order to prevent the surplus power consumptions. Meanwhile, we have designed the extendible register for storing, detecting, and examining the pulse converter binary data produced repeatedly. Then shift and filter the binary data to calculate the cycle and pulsewidth of the clock signal with new register. Finally, use mapping table to transfer the desired value which produce new pulsewidth, can lock pulse signal on 20%、30%、40%、50%、60% 、70% 、80% pulsewidth, respectively. We finished the IC layout and the parameter extraction in TSMC 0.18-um CMOS 1.8-V technology. The post-layout simulation shows that our new architecture can work in high-speed clock frequency ranging from 300-MHz to 550-MHz, and the pulsewidth can be locked from 20% to 80% duty cycle, successfully. The chip area of the main circuit is only about 277- μm × 270- μm .