Adders are crucial components used digit circuits, many improvements has been made to refine the design of an adder. In this paper, an inverted gate diffusion input (IGDI) scheme is proposed. Instead of using standard CMOS logic gates, a hybrid CMOS/IGDI scheme is adopted in a full adder
design. The hybrid scheme not only reduces the number of MOSs required in a full adder, but also maintain its performance. In addition, the propose hybrid CMOS/IGDI architecture is scalable to meet large adder design. In short, the proposed hybrid CMOS/IGDI adder architecture can be taken as a better alternative adder design.