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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/14270

    Title: A 16 Bit Adder/Subtractor using hybrid IGDI/CMOS design
    Authors: Po-Ming Lee
    Yun-Hsiun Hung
    Wen-Pin Chen
    Keywords: CMOS
    Inverted Gate Diffusion Input
    Full Adder
    Date: 2007-09-28
    Issue Date: 2007-10-01 15:56:30 (UTC+8)
    Abstract: Adders are crucial components used digit circuits, many improvements has been made to refine the design of an adder. In this paper, an inverted gate diffusion input (IGDI) scheme is proposed. Instead of using standard CMOS logic gates, a hybrid CMOS/IGDI scheme is adopted in a full adder
    design. The hybrid scheme not only reduces the number of MOSs required in a full adder, but also maintain its performance. In addition, the propose hybrid CMOS/IGDI architecture is scalable to meet large adder design. In short, the proposed hybrid CMOS/IGDI adder architecture can be taken as a better alternative adder design.
    Appears in Collections:[電子工程系所] 2007年系統雛型與電路設計創新應用研討會

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