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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/14269


    Title: A New Sub-1 V Low-Power CMOS Adder Core
    Authors: Yu-Cherng Hung
    Chiou-Kou Tung
    Shao-Hui Shieh
    Bo-Yuan Shieh
    Date: 2007-09-28
    Issue Date: 2007-10-01 15:53:25 (UTC+8)
    Abstract: In this paper, a new low-voltage low-power CMOS adder core is proposed. Without using special CMOS technologies, the circuit can be operated within 0.9 V supply voltage by utilizations of charge pumping and body littleforward-bias techniques. The low-voltage operation is an important issue in deep submicron CMOS technologies especially for ‘reliability’ consideration. The circuit is designed by TSMC 0.35 μm CMOS technology. SPICE simulations show that the circuit operates successfully 25 MHz in 0.9 V supply and average power dissipation is 1.27 μW.
    Appears in Collections:[電子工程系所] 2007年系統雛型與電路設計創新應用研討會

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