In this paper, a new low-voltage low-power CMOS adder core is proposed. Without using special CMOS technologies, the circuit can be operated within 0.9 V supply voltage by utilizations of charge pumping and body littleforward-bias techniques. The low-voltage operation is an important issue in deep submicron CMOS technologies especially for ‘reliability’ consideration. The circuit is designed by TSMC 0.35 μm CMOS technology. SPICE simulations show that the circuit operates successfully 25 MHz in 0.9 V supply and average power dissipation is 1.27 μW.