This paper presents a digital anti-windup IP controller using a field programmable gate array (FPGA) device to improve the dynamic performance of the switched reluctance motor (SRM). Traditionally, the PI controller is designed for operating in the linear region. The windup phenomenon will occur when the output of the PI controller is saturated.
The proposed method is then developed to reduce the degradation in the system
performance due to saturation. When the output of the IP controller is saturated, the integral state is reset to zero with a rate of the integral time constant by negatively feeding back the controller output. The dynamic characteristics of overshoot, settling time, and load disturbance rejection can then be improved. In addition, the proposed SRM based drive system was implemented by using a digital FPGA scheme to improve the drawback of the analog circuit method. Comparisons have been made to the conventional IP and anti-windup PI controllers. Results show that the proposed anti-windup IP controller outperforms the others methods in terms of overshoot, settling time, and load disturbance rejection.
International Journal OF ELECTRICAL ENGINEERING, VOL.17, NO.3 PP.189-197 (2010)