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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/12896


    Title: 電源nLDMOS元件源/汲極工程探討研究
    Authors: 陳勝利;吳宗賢;陳勛祥
    Contributor: 電機工程系
    Keywords: 靜電放電;閂鎖效應;觸發電壓;保持電壓;臨界電壓;適應層
    Electrostatic Discharge;Latch-up effect;Trigger Voltage;Holding Voltage;threshold voltage;adaptive layer
    Date: 2010-12-03
    Issue Date: 2010-12-16 15:27:59 (UTC+8)
    Publisher: 台南縣:崑山科技大學
    Abstract: 本篇論文,我們主要是針對高壓元件 nLDMOS 的閂鎖
    效應(Latch-up)可靠性問題進行改善研究,也就是利用源
    極(Source)工程改善該元件閂鎖效應。有兩個重要物理
    參數分別是保持電壓(Holding Voltage) 和觸發電壓
    (Trigger Voltage)可用來判斷此高壓元件對於閂鎖問題
    的免疫力和實際應用上的導通速度。本次研究結果最後
    可得個結論:源極/汲極工程可有效地使觸發電壓降低和
    保持電壓的提升,可有效地使閂鎖效應得到改善。
    For the HV device latch-up reliability problem, both drain-side and source-side engineering by adding Nad and Pad layers to obtain a weak snapback characteristic nLDMOS are investigated in this work. It is a novel method to reduce trigger voltage(Vt1) and to increase holding voltage(Vh) for the latch-up immunity and turn-on speed. These efforts will be very suitable for the HV power management IC applications. From this work, it is can be concluded that the trigger voltage and holding voltage of an HV nLDMOS device can be more effective improved by the source/drain-side engineering.
    Relation: 第31屆電力工程研討會
    Appears in Collections:[電機工程系所 ] 2010第卅一屆電力工程研討會

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