本篇論文，我們主要是針對高壓元件 nLDMOS 的閂鎖
參數分別是保持電壓(Holding Voltage) 和觸發電壓
For the HV device latch-up reliability problem, both drain-side and source-side engineering by adding Nad and Pad layers to obtain a weak snapback characteristic nLDMOS are investigated in this work. It is a novel method to reduce trigger voltage(Vt1) and to increase holding voltage(Vh) for the latch-up immunity and turn-on speed. These efforts will be very suitable for the HV power management IC applications. From this work, it is can be concluded that the trigger voltage and holding voltage of an HV nLDMOS device can be more effective improved by the source/drain-side engineering.