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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/12207

    Title: A Novel Method for Real-Time Tracer Data Sequence Compression of FPGA-Based SoC On-Chip Debugger
    SoC 晶片內部除錯器的即時資料壓縮技術
    Authors: 蔡國瑞;Guo-Ruey Tsai
    林明權;Min-Chuan Lin
    Contributor: 電子工程系
    Keywords: SoC (System on Chip)
    logic state tracer
    FPGA (Field Programmable Gate Array)
    on-chip debugger
    Date: 2007-07
    Issue Date: 2010-12-03 16:24:35 (UTC+8)
    Publisher: 崑山科技大學
    Abstract: We have presented a two-level tracer data compressor design with pipeline structure for
    real-time data sequences compression of FPGA-based SoC on-chip debugger. A
    counter-based coarse level compression process is used for continuously repeating tracer data
    sequences, and the following fine level compression processes, including both fixed-length
    real-time fine compression and variable-length fine compression, are proposed to further
    compress the similarity bits between two neighbor tracer data of the de-repeated tracer data
    sequence. The two-level tracer data compressor not only is synchronous with the tracer
    sampling clock rate, but also needs less synthesized chip area. The compression ratio of such
    tracer data compressor is very high up to 100 times dependent of the tracer data channel
    arrangement. By the parametric hardware-description language module design, we can
    reconfigure flexible tracer data channel and data storage structure in order to match with
    different system requirements.
    Relation: 崑山科技大學學報第四期 第1~10 頁(民國96 年7 月)
    Journal of Kun Shan University, Vol.4, pp.1~10(Jul, 2007)
    Appears in Collections:[崑山科技大學學報] 第4期

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