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    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/12123


    Title: A novel CMOS process compatible high performance parallel-stacked RF spiral inductor
    Authors: D. K. Jair(翟大鈞)
    Ming Chun Hsieh(謝明君)
    C. S. Lin
    Contributor: 機械工程系
    Date: 2010-11-26
    ISSN: 0946-7076
    Issue Date: 2010-11-29 16:40:19 (UTC+8)
    Abstract: In this study, a deep-submicron CMOS process
    compatible parallel-stacked inductor has been successfully
    developed. We use the mature CMOS compatible technology
    and air gap structure to reduce substrate losses and
    parallel-stacked structure to reduce the resistance, thus can
    promote the Q factor. Experimental results evidence that
    by using the parallel-stacked structure, the chip area can be
    reduced significantly for the issue of continuing reduction
    of the chip size. Furthermore, the resistance can be reduced
    by using the parallel-stacked structure and thus results in an
    obviously improving of the Q at low frequency. The
    measured peak Q and peak-Q frequency with the parallel
    metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz,
    thus enhancing its applications for higher frequency RF IC.
    Therefore, the developed deep-submicron CMOS process
    compatible parallel-stacked inductor is suitable for CMOS
    RF integrated circuit applications.
    Relation: Microsystem Technologies (2010) 16:1175–1179
    Appears in Collections:[機械工程系所] 期刊論文

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