English  |  正體中文  |  简体中文  |  Items with full text/Total items : 26653/27249 (98%)
Visitors : 12253341      Online Users : 418
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ksu.edu.tw/handle/987654321/11141


    Title: 基於CMOS動態邏輯電路之高速可程式除頻晶片的研製
    其他題名: Implementation of CMOS Programmable Divider Chips Base on the Dynamic Logic Circuit
    Authors: 許瀞文
    Ching-Wen Hsu
    Contributors: 盧春林
    Keywords: 除頻器
    Frequency Divider
    Date: 2010
    Issue Date: 2010-10-07 16:13:28 (UTC+8)
    Abstract: 本論文提出一新型動態邏輯架構,以讓可程式邏輯電路的工作速度得以升級到GHz。論文內容除了說明新型動態邏輯的架構與設計重點,也和傳統數位邏輯電路架構、以及CML數位電路架構做比較,以顯現本論文所提出的動態邏輯電路在可程式邏輯方面的優勢。
    本論文也使用Agilent的ADS(Advanced Design System)模擬軟體,以及分別使用TSMC 0.18 μm 1P6M CMOS製程、和TSMC 90 nm 1P9M CMOS製程,將本論文所提出的新型動態邏輯架構,分別應用在12 GHz除二的除頻器,以及可程式除二/除四的24 GHz除頻器上面,以驗證所提出之電路架構的可行性。TT之模擬結果顯示,在1.8 V的電壓供應下,0.18 μm除頻器可工作之頻率範圍為6 - 12 GHz,核心電路消耗9.77 mW,buffer電路消耗32 mW,12 GHz時靈敏度為0.045 V,此時輸出電壓為0.27 V。24 GHz除二/除四之除頻器在1.2 VDC之下,除二模式可操作在4-24 GHz,24GHz時輸出功率為 -11.9 dBm;除四模式可操作在 20–29 GHz,24 GHz時輸出功率為 -0.9 dBm。
    This paper proposes a novel dynamic logic circuit architecture to let the programmable logic circuit be able to work up to the speed of GHz. Except describing the working principle of the proposed dynamic logic circuit, it is compared with the traditional logic circuits, such as the basic CMOS pair logic circuit and CML logic circuit, to highlight the merit of it.
    Two frequency dividers are carefully simulated under ADS (Advanced Design System) of Agilent with TSMC 0.18 μm CMOS 1P6M process and TSMC 90 nm CMOS 1P9M process respectively to show that the proposed circuit architecture is practicable. One of them is the 12 GHz divide-by-two frequency divider in 0.18 μm process. The other one is the 24 GHz divide-by-two or divide-by-four frequency divider in 90 nm process.
    The simulation results show that the frequency divider designed in TSMC 0.18 μm CMOS process, with a 1.8 V DC power connected, has a working range of 6-12 GHz, a core circuit power consumption of 9.77 mW, and a total power consumption of 32 mW. The input sensitivity is simulated under 12 GHz to be 0.045 V while the output voltage will be 0.27 V. On the other hand, the 24 GHz frequency divider has a working range of 4-24 GHz and will offer -11.9 dBm output power at 12 GHz in divide-by-two mode. Meanwhile, its working range becomes 20-29 GHz and offers -0.9 dBm output power at 24 GHz in divide-by-four mode.
    Appears in Collections:[資訊工程系所] 博碩士論文

    Files in This Item:

    File Description SizeFormat
    ksu-99-G980A003-1.pdf4385KbAdobe PDF281View/Open


    All items in KSUIR are protected by copyright, with all rights reserved.


    本網站之所有圖文內容授權為崑山科技大學圖書資訊館所有,請勿任意轉載或擷取使用。
    ©Kun Shan University Library and Information Center
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback